Kernel Architecture

Rumpk uses a four-layer architecture where each layer has a strict responsibility boundary.

The Four Layers

┌──────────────────────────────────┐
│  NPL / NPK  (Applications)      │  User Mode
│  Isolated fibers, sandboxed      │
├──────────────────────────────────┤
│  ABI Layer (SysTable)            │  Fixed contract
│  12 syscalls + 1 meta-slot       │  240 bytes
├──────────────────────────────────┤
│  Rumpk (Kernel Logic)            │  Supervisor Mode
│  Scheduler, Memory, NetSwitch    │  Nim
├──────────────────────────────────┤
│  HAL (Hardware Abstraction)      │  Machine Mode
│  VirtIO, UART, GIC, Timer, MMU   │  Zig
├──────────────────────────────────┤
│  Rumkv (Hypervisor)              │  Highest Privilege
│  EL2 / Ring-1 / M-Mode           │  Optional
└──────────────────────────────────┘

SysTable — The Frozen ABI

The SysTable is a fixed 240-byte structure at a known physical address:

• RISC-V: 0x83000000
• ARM64: 0x50000000

It contains pointers to exactly 12 syscall entry points plus 1 meta-slot. This ABI is frozen — it never changes across versions. Any NPL compiled against this ABI will work on any Rumpk version.

SMP — Message-Passing, Not Mutexes

Rumpk adopts the DragonflyBSD LWKT (Lightweight Kernel Threads) model for symmetric multiprocessing:

• CPU cores are isolated domains
• Data moves between cores via messages, not shared memory
• No mutexes, no spinlocks, no lock contention
• Linear scaling to 256+ cores

This means: data moves, code stays. A fiber runs on one core. If it needs something from another core, it sends a message through an ION Ring.

Memory Model — Cellular Memory

Memory is divided into two regions:

• Bridgehead: Fixed kernel memory, identity-mapped. Contains the SysTable, scheduler state, and ION Ring descriptors.
• Wild: Dynamic memory for fiber stacks, NPL heaps, and DMA buffers. Protected by PMP (Physical Memory Protection) on RISC-V or MPU on ARM64.

Each fiber gets its own memory partition. One fiber cannot access another's memory without an explicit capability grant.

Interrupt Architecture

Interrupts are handled in a two-phase model:

1. Phase 1 (Zig HAL): The interrupt vector catches the hardware event, acknowledges it (GIC claim on ARM64, PLIC claim on RISC-V), and pushes a minimal event descriptor onto the appropriate ION Ring.
2. Phase 2 (Nim Logic): The scheduler picks up the event and dispatches it to the correct fiber for processing.

This separation means interrupt handling is deterministic — the Zig layer does the absolute minimum, and all logic runs in the scheduler's cooperative context.

Privilege Modes

Rumpk uses hardware privilege modes for isolation:

Mode	RISC-V	ARM64	Role
Highest	M-Mode	EL2	Rumkv hypervisor
Supervisor	S-Mode	EL1	Rumpk kernel
User	U-Mode	EL0	NPL/NPK applications

Transitions between modes go through the SysTable — the only gate between privilege levels.